Automatic formal verification of systolic array designs

Keyphrases

• Array Design 100%
• Prolog 100%
• Systolic Array 100%
• Automated Verification 100%
• Verification Method 66%
• Systolic Architecture 66%
• Efficiency Improvement 33%
• Formal Specification 33%
• Design Verification 33%
• User Control 33%
• Matching Mechanism 33%
• Formal Verification 33%
• Verifier 33%
• Pattern Matching 33%
• Induction Techniques 33%
• Efficient Verification 33%
• Levels of Abstraction 33%
• Difference Equations 33%
• Interval Temporal Logic 33%
• New Formalism 33%
• Verification Strategy 33%
• Formal Design 33%
• Arithmetic Difference 33%
• Formal Techniques 33%

Computer Science

• Formal Verification 100%
• Systolic Arrays 100%
• Formal Specification 33%
• Design Verification 33%
• Backtracking 33%
• Pattern Matching 33%
• Temporal Logic 33%