Soft error is one critical issue faced by nano-scale random access memories (RAMs). Three-dimensional (3D) RAM with through-silicon via (TSV) is a new approach for overcoming the memory wall. A 3D RAM consists of multiple dies vertically stacked. Therefore, the upper die provides the shielding effect for the lower die. Thus, the SER in the upper die is higher than that in the lower die. This paper proposes an area and reliability efficient ECC (ARE-ECC) scheme for 3D RAMs by taking advantage of the shielding effect. An area and reliability optimization algorithm is also proposed to aid the designer to design the ARE-ECC scheme for 3D RAMs. Simulation results show that the ARE-ECC scheme can effectively increase the reliability of a 3D RAM using small area overhead.