Application of hardware architecture of genetic algorithm for optimal packet scheduling

Rong Hou Wu; Yang Han Lee; Shiann Tsong Sheu; Hsien Wei Tseng; Ming Hsueh Chuang; Yung Kuang Wang

doi:10.2991/jcis.2006.299

Application of hardware architecture of genetic algorithm for optimal packet scheduling

Rong Hou Wu, Yang Han Lee, Shiann Tsong Sheu, Hsien Wei Tseng, Ming Hsueh Chuang, Yung Kuang Wang

Department of Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In Dense Wavelength Division Multiplexing (DWDM) technologies, the optimal packet scheduling is a common encounter issue in multiple channels network. NP-hard problem deals with finding a way to rearrange packets in multiple channels into a finite and rare channel. Genetic algorithm (GA) is one of the most efficient ways to solve this issue. We hope to find a better solution to our task through the GA characteristics of multiprocessor searching and survivor of the fittest. Therefore, a modified and achievable hardware architecture of GA is presented in this paper. This architecture can increase the schedule speed of packet scheduling also can promote the efficiency of DWDM in Optical Communication Networks.

Original language	English
Title of host publication	Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006
DOIs	https://doi.org/10.2991/jcis.2006.299
State	Published - 2006
Event	9th Joint Conference on Information Sciences, JCIS 2006 - Taiwan, ROC, Taiwan Duration: 8 Oct 2006 → 11 Oct 2006

Publication series

Name	Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006
Volume	2006

Conference

Conference	9th Joint Conference on Information Sciences, JCIS 2006
Country/Territory	Taiwan
City	Taiwan, ROC
Period	8/10/06 → 11/10/06

Keywords

Dense wavelength division multiplexing
Genetic algorithm
Packet scheduling

Access to Document

10.2991/jcis.2006.299

Cite this

Wu, R. H., Lee, Y. H., Sheu, S. T., Tseng, H. W., Chuang, M. H., & Wang, Y. K. (2006). Application of hardware architecture of genetic algorithm for optimal packet scheduling. In Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006 Article FTT-77 (Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006; Vol. 2006). https://doi.org/10.2991/jcis.2006.299

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title = "Application of hardware architecture of genetic algorithm for optimal packet scheduling",

abstract = "In Dense Wavelength Division Multiplexing (DWDM) technologies, the optimal packet scheduling is a common encounter issue in multiple channels network. NP-hard problem deals with finding a way to rearrange packets in multiple channels into a finite and rare channel. Genetic algorithm (GA) is one of the most efficient ways to solve this issue. We hope to find a better solution to our task through the GA characteristics of multiprocessor searching and survivor of the fittest. Therefore, a modified and achievable hardware architecture of GA is presented in this paper. This architecture can increase the schedule speed of packet scheduling also can promote the efficiency of DWDM in Optical Communication Networks.",

keywords = "Dense wavelength division multiplexing, Genetic algorithm, Packet scheduling",

author = "Wu, {Rong Hou} and Lee, {Yang Han} and Sheu, {Shiann Tsong} and Tseng, {Hsien Wei} and Chuang, {Ming Hsueh} and Wang, {Yung Kuang}",

year = "2006",

doi = "10.2991/jcis.2006.299",

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isbn = "9078677015",

series = "Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006",

booktitle = "Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006",

note = "9th Joint Conference on Information Sciences, JCIS 2006 ; Conference date: 08-10-2006 Through 11-10-2006",

}

Wu, RH, Lee, YH, Sheu, ST, Tseng, HW, Chuang, MH & Wang, YK 2006, Application of hardware architecture of genetic algorithm for optimal packet scheduling. in Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006., FTT-77, Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006, vol. 2006, 9th Joint Conference on Information Sciences, JCIS 2006, Taiwan, ROC, Taiwan, 8/10/06. https://doi.org/10.2991/jcis.2006.299

Application of hardware architecture of genetic algorithm for optimal packet scheduling. / Wu, Rong Hou; Lee, Yang Han; Sheu, Shiann Tsong et al.
Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006. 2006. FTT-77 (Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Application of hardware architecture of genetic algorithm for optimal packet scheduling

AU - Wu, Rong Hou

AU - Lee, Yang Han

AU - Sheu, Shiann Tsong

AU - Tseng, Hsien Wei

AU - Chuang, Ming Hsueh

AU - Wang, Yung Kuang

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N2 - In Dense Wavelength Division Multiplexing (DWDM) technologies, the optimal packet scheduling is a common encounter issue in multiple channels network. NP-hard problem deals with finding a way to rearrange packets in multiple channels into a finite and rare channel. Genetic algorithm (GA) is one of the most efficient ways to solve this issue. We hope to find a better solution to our task through the GA characteristics of multiprocessor searching and survivor of the fittest. Therefore, a modified and achievable hardware architecture of GA is presented in this paper. This architecture can increase the schedule speed of packet scheduling also can promote the efficiency of DWDM in Optical Communication Networks.

AB - In Dense Wavelength Division Multiplexing (DWDM) technologies, the optimal packet scheduling is a common encounter issue in multiple channels network. NP-hard problem deals with finding a way to rearrange packets in multiple channels into a finite and rare channel. Genetic algorithm (GA) is one of the most efficient ways to solve this issue. We hope to find a better solution to our task through the GA characteristics of multiprocessor searching and survivor of the fittest. Therefore, a modified and achievable hardware architecture of GA is presented in this paper. This architecture can increase the schedule speed of packet scheduling also can promote the efficiency of DWDM in Optical Communication Networks.

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T2 - 9th Joint Conference on Information Sciences, JCIS 2006

Y2 - 8 October 2006 through 11 October 2006

ER -

Application of hardware architecture of genetic algorithm for optimal packet scheduling

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