Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

Cihun Siyong Alex Gong; Muh Tian Shiue; Ci Tong Hong; Chun Hsien Su; Kai Wen Yao

doi:10.1109/SOCC.2007.4545468

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

Cihun Siyong Alex Gong, Muh Tian Shiue, Ci Tong Hong, Chun Hsien Su, Kai Wen Yao

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.

Original language	English
Title of host publication	Proceedings - 20th Anniversary IEEE International SOC Conference
Pages	247-250
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545468
State	Published - 2007
Event	20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan Duration: 26 Sep 2007 → 29 Sep 2007

Publication series

Name	Proceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference	20th Anniversary IEEE International SOC Conference
Country/Territory	Taiwan
City	Hsinchu
Period	26/09/07 → 29/09/07

Access to Document

10.1109/SOCC.2007.4545468

Cite this

Gong, C. S. A., Shiue, M. T., Hong, C. T., Su, C. H., & Yao, K. W. (2007). Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications. In Proceedings - 20th Anniversary IEEE International SOC Conference (pp. 247-250). Article 4545468 (Proceedings - 20th Anniversary IEEE International SOC Conference). https://doi.org/10.1109/SOCC.2007.4545468

@inproceedings{016391b707f241dc9dfd35da869ba710,

title = "Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications",

abstract = "A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.",

author = "Gong, {Cihun Siyong Alex} and Shiue, {Muh Tian} and Hong, {Ci Tong} and Su, {Chun Hsien} and Yao, {Kai Wen}",

year = "2007",

doi = "10.1109/SOCC.2007.4545468",

language = "???core.languages.en_GB???",

isbn = "9781424415922",

series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

pages = "247--250",

booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",

note = "20th Anniversary IEEE International SOC Conference ; Conference date: 26-09-2007 Through 29-09-2007",

}

Gong, CSA, Shiue, MT, Hong, CT, Su, CH & Yao, KW 2007, Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications. in Proceedings - 20th Anniversary IEEE International SOC Conference., 4545468, Proceedings - 20th Anniversary IEEE International SOC Conference, pp. 247-250, 20th Anniversary IEEE International SOC Conference, Hsinchu, Taiwan, 26/09/07. https://doi.org/10.1109/SOCC.2007.4545468

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications. / Gong, Cihun Siyong Alex; Shiue, Muh Tian; Hong, Ci Tong et al.
Proceedings - 20th Anniversary IEEE International SOC Conference. 2007. p. 247-250 4545468 (Proceedings - 20th Anniversary IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

AU - Gong, Cihun Siyong Alex

AU - Shiue, Muh Tian

AU - Hong, Ci Tong

AU - Su, Chun Hsien

AU - Yao, Kai Wen

PY - 2007

Y1 - 2007

N2 - A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.

AB - A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.

UR - http://www.scopus.com/inward/record.url?scp=51049120691&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2007.4545468

DO - 10.1109/SOCC.2007.4545468

M3 - 會議論文篇章

AN - SCOPUS:51049120691

SN - 9781424415922

T3 - Proceedings - 20th Anniversary IEEE International SOC Conference

SP - 247

EP - 250

BT - Proceedings - 20th Anniversary IEEE International SOC Conference

T2 - 20th Anniversary IEEE International SOC Conference

Y2 - 26 September 2007 through 29 September 2007

ER -

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this