An IP-based design to achieve power reduction

Chin Fa Hsieh, Tsung Han Tsai, Chih Hung Lai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this chapter, an IP-based design for power reduction on a one- dimension, lifting-based discrete wavelet transform (DWT) is presented. The prototype architecture is coded in VerilogHDL and simulated using Quartus-II to verify the function. Based on this prototype architecture, a low-power operator (adder and subtractor) IP, which is designed based on a full-custom design methodology, plays a role in replacing the main operations. The simulation result shows that power consumption can be reduced by 16.31%. The architecture can be used as an independent IP core of a wavelet-based application.

Original languageEnglish
Title of host publicationProceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
EditorsJengnan Juang
PublisherSpringer Verlag
Pages493-499
Number of pages7
ISBN (Print)9783319173139
DOIs
StatePublished - 2016
Event3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan
Duration: 19 Dec 201421 Dec 2014

Publication series

NameLecture Notes in Electrical Engineering
Volume345
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Conference

Conference3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Country/TerritoryTaiwan
CityKaohsiung
Period19/12/1421/12/14

Keywords

  • Discrete wavelet transform
  • IP
  • VerilogHDL

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