An infrastructure IP for repairing multiple RAMs in SOCs

Chao Da Huang; Tsu Wei Tseng; Jin Fu Li

doi:10.1109/VDAT.2006.258150

An infrastructure IP for repairing multiple RAMs in SOCs

Chao Da Huang, Tsu Wei Tseng, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories based on TSMC 0.18μm standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%.

Original language	English
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages	163-166
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2006.258150
State	Published - 2007
Event	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan Duration: 26 Apr 2007 → 28 Apr 2007

Publication series

Name	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Country/Territory	Taiwan
City	Hsinchu
Period	26/04/07 → 28/04/07

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10.1109/VDAT.2006.258150

Cite this

Huang, C. D., Tseng, T. W., & Li, J. F. (2007). An infrastructure IP for repairing multiple RAMs in SOCs. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 163-166). Article 4027522 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258150

@inproceedings{8069dccf10b143bca98ac86ef0593612,

title = "An infrastructure IP for repairing multiple RAMs in SOCs",

abstract = "Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories based on TSMC 0.18μm standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%.",

author = "Huang, {Chao Da} and Tseng, {Tsu Wei} and Li, {Jin Fu}",

year = "2007",

doi = "10.1109/VDAT.2006.258150",

language = "???core.languages.en_GB???",

isbn = "1424401798",

series = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

pages = "163--166",

booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 ; Conference date: 26-04-2007 Through 28-04-2007",

}

Huang, CD, Tseng, TW & Li, JF 2007, An infrastructure IP for repairing multiple RAMs in SOCs. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027522, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 163-166, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 26/04/07. https://doi.org/10.1109/VDAT.2006.258150

An infrastructure IP for repairing multiple RAMs in SOCs. / Huang, Chao Da; Tseng, Tsu Wei; Li, Jin Fu.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 163-166 4027522 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An infrastructure IP for repairing multiple RAMs in SOCs

AU - Huang, Chao Da

AU - Tseng, Tsu Wei

AU - Li, Jin Fu

PY - 2007

Y1 - 2007

N2 - Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories based on TSMC 0.18μm standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%.

AB - Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories based on TSMC 0.18μm standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%.

UR - http://www.scopus.com/inward/record.url?scp=34748823567&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2006.258150

DO - 10.1109/VDAT.2006.258150

M3 - 會議論文篇章

AN - SCOPUS:34748823567

SN - 1424401798

SN - 9781424401796

T3 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

SP - 163

EP - 166

BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006

Y2 - 26 April 2007 through 28 April 2007

ER -

Huang CD, Tseng TW, Li JF. An infrastructure IP for repairing multiple RAMs in SOCs. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 163-166. 4027522. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2006.258150

An infrastructure IP for repairing multiple RAMs in SOCs

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