An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Chih Sheng Hou; Jin Fu Li; Chih Yen Lo; Ding Ming Kwai; Yung Fa Chou; Cheng Wen Wu

doi:10.1109/VLDI-DAT.2013.6533853

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Chih Sheng Hou, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533853
State	Published - 2013
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan Duration: 22 Apr 2013 → 24 Apr 2013

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/13 → 24/04/13

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10.1109/VLDI-DAT.2013.6533853

Cite this

Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F., & Wu, C. W. (2013). An FPGA-based test platform for analyzing data retention time distribution of DRAMs. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 Article 6533853 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533853

@inproceedings{effabb9feed44cea9d40b32c445e8b98,

title = "An FPGA-based test platform for analyzing data retention time distribution of DRAMs",

abstract = "Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.",

author = "Hou, {Chih Sheng} and Li, {Jin Fu} and Lo, {Chih Yen} and Kwai, {Ding Ming} and Chou, {Yung Fa} and Wu, {Cheng Wen}",

year = "2013",

doi = "10.1109/VLDI-DAT.2013.6533853",

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isbn = "9781467344357",

series = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

note = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

}

Hou, CS, Li, JF, Lo, CY, Kwai, DM, Chou, YF & Wu, CW 2013, An FPGA-based test platform for analyzing data retention time distribution of DRAMs. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533853, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, 22/04/13. https://doi.org/10.1109/VLDI-DAT.2013.6533853

An FPGA-based test platform for analyzing data retention time distribution of DRAMs. / Hou, Chih Sheng; Li, Jin Fu; Lo, Chih Yen et al.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533853 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Jin Fu

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AU - Kwai, Ding Ming

AU - Chou, Yung Fa

AU - Wu, Cheng Wen

PY - 2013

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N2 - Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

AB - Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

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BT - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

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Y2 - 22 April 2013 through 24 April 2013

ER -

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

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