An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration

Shyh Shyuan Sheu; Zhe Hui Lin; Jui Feng Hung; John H. Lau; Peng Shu Chen; Shih Hsien Wu; Keng Li Su; Chih Sheng Lin; Shinn Juh Lai; Kuo Hsing Cheng; Tzu Kun Ku; Wei Chung Lo; Ming Jer Kao

doi:10.4071/imaps.307

An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration

Shyh Shyuan Sheu, Zhe Hui Lin, Jui Feng Hung, John H. Lau, Peng Shu Chen, Shih Hsien Wu, Keng Li Su, Chih Sheng Lin, Shinn Juh Lai, Kuo Hsing Cheng, Tzu Kun Ku, Wei Chung Lo, Ming Jer Kao

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

Original language	English
Pages (from-to)	140-145
Number of pages	6
Journal	Journal of Microelectronics and Electronic Packaging
Volume	8
Issue number	4
DOIs	https://doi.org/10.4071/imaps.307
State	Published - 2011

Keywords

3D IC integration
TSV electrical testing method and guidelines
Through silicon via (TSV)

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title = "An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration",

abstract = "This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.",

keywords = "3D IC integration, TSV electrical testing method and guidelines, Through silicon via (TSV)",

author = "Sheu, {Shyh Shyuan} and Lin, {Zhe Hui} and Hung, {Jui Feng} and Lau, {John H.} and Chen, {Peng Shu} and Wu, {Shih Hsien} and Su, {Keng Li} and Lin, {Chih Sheng} and Lai, {Shinn Juh} and Cheng, {Kuo Hsing} and Ku, {Tzu Kun} and Lo, {Wei Chung} and Kao, {Ming Jer}",

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AU - Sheu, Shyh Shyuan

AU - Lin, Zhe Hui

AU - Hung, Jui Feng

AU - Lau, John H.

AU - Chen, Peng Shu

AU - Wu, Shih Hsien

AU - Su, Keng Li

AU - Lin, Chih Sheng

AU - Lai, Shinn Juh

AU - Cheng, Kuo Hsing

AU - Ku, Tzu Kun

AU - Lo, Wei Chung

AU - Kao, Ming Jer

PY - 2011

Y1 - 2011

N2 - This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

AB - This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

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KW - TSV electrical testing method and guidelines

KW - Through silicon via (TSV)

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M3 - 期刊論文

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An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration

Abstract

Keywords

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