An efficient IP-level power model for complex digital circuits

Chih Yang Hsu, Chien Nan Jimmy Liu, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, we propose an efficient IP-level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power, to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages610-613
Number of pages4
ISBN (Electronic)0780376595
DOIs
StatePublished - 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 21 Jan 200324 Jan 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
Country/TerritoryJapan
CityKitakyushu
Period21/01/0324/01/03

Fingerprint

Dive into the research topics of 'An efficient IP-level power model for complex digital circuits'. Together they form a unique fingerprint.

Cite this