An efficient IP-level power model for complex digital circuits

Chih Yang Hsu; Chien Nan Jimmy Liu; Jing Yang Jou

doi:10.1109/ASPDAC.2003.1195097

An efficient IP-level power model for complex digital circuits

Chih Yang Hsu, Chien Nan Jimmy Liu, Jing Yang Jou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, we propose an efficient IP-level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power, to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	610-613
Number of pages	4
ISBN (Electronic)	0780376595
DOIs	https://doi.org/10.1109/ASPDAC.2003.1195097
State	Published - 2003
Event	Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan Duration: 21 Jan 2003 → 24 Jan 2003

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2003-January

Conference

Conference	Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Country/Territory	Japan
City	Kitakyushu
Period	21/01/03 → 24/01/03

Access to Document

10.1109/ASPDAC.2003.1195097

Cite this

Hsu, C. Y., Liu, C. N. J., & Jou, J. Y. (2003). An efficient IP-level power model for complex digital circuits. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 610-613). [1195097] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195097

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abstract = "In this paper, we propose an efficient IP-level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power, to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.",

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Hsu, CY, Liu, CNJ & Jou, JY 2003, An efficient IP-level power model for complex digital circuits. in Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference., 1195097, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 610-613, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 21/01/03. https://doi.org/10.1109/ASPDAC.2003.1195097

An efficient IP-level power model for complex digital circuits. / Hsu, Chih Yang; Liu, Chien Nan Jimmy; Jou, Jing Yang.

Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. p. 610-613 1195097 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we propose an efficient IP-level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power, to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.

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Hsu CY, Liu CNJ, Jou JY. An efficient IP-level power model for complex digital circuits. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2003. p. 610-613. 1195097. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2003.1195097

An efficient IP-level power model for complex digital circuits

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