An effective physical synthesis technique for multiplier

Cheng Yeh Wang, Ya Chi Yang, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents an effective multiplier synthesis algorithm for cell-based multipliers. By using a novel tree generation algorithm with timing consideration for each vertical compressor slice(VCS), our synthesizer generates multipliers automatically with very promising results.

Original languageEnglish
Title of host publicationVLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages192-195
Number of pages4
ISBN (Electronic)0780377656
DOIs
StatePublished - 2003
Event20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 - Hsinchu, Taiwan
Duration: 6 Oct 20038 Oct 2003

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume2003-January
ISSN (Print)1930-8868

Conference

Conference20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003
Country/TerritoryTaiwan
CityHsinchu
Period6/10/038/10/03

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