An Area-Efficient and High Throughput Hardware Implementation of Exponent Function

Muhammad Awais Hussain, Shung Wei Lin, Tsung Han Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, an area-efficient and high throughput hardware implementation of the exponent function has been proposed. The proposed exponent calculation method eliminates the memory requirements leading to power and area savings. The pipelined hardware implementation results in a high-frequency design with reduced resources usage. The hardware implementation has been performed for Xilinx Virtex-4 FPGA board and TSMC 90nm process node. The throughput of 411.3 Mbps at 115.7 MHz frequency and 711.11 Mbps at 200 MHz frequency can be achieved for FPGA and ASIC design, respectively. The power consumption is 242mW and 6.1 mW for FPGA and ASIC platforms, respectively.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3369-3372
Number of pages4
ISBN (Electronic)9781665484855
DOIs
StatePublished - 2022
Event2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States
Duration: 27 May 20221 Jun 2022

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2022-May
ISSN (Print)0271-4310

Conference

Conference2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/TerritoryUnited States
CityAustin
Period27/05/221/06/22

Keywords

  • Digital design
  • Exponent function
  • FPGA
  • Hardware accelerator
  • VLSI

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