An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

Wei Chang, Yu Guang Chen, Po Yeh Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

Original languageEnglish
Title of host publication34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
EditorsLuigi Dilillo, Luca Cassano, Athanasios Papadimitriou
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665416092
DOIs
StatePublished - 2021
Event34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 - Virtual, Athens, Greece
Duration: 6 Oct 20218 Oct 2021

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume2021-October
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
Country/TerritoryGreece
CityVirtual, Athens
Period6/10/218/10/21

Keywords

  • 8T SRAM
  • In-Memory Computing
  • PBTI
  • supplemental transistor

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