An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

Wei Chang; Yu Guang Chen; Po Yeh Huang; Jin Fu Li

doi:10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

Wei Chang, Yu Guang Chen, Po Yeh Huang, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

Original language	English
Title of host publication	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
Editors	Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665416092
DOIs	https://doi.org/10.1109/DFT52944.2021.9568343
State	Published - 2021
Event	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 - Virtual, Athens, Greece Duration: 6 Oct 2021 → 8 Oct 2021

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume	2021-October
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
Country/Territory	Greece
City	Virtual, Athens
Period	6/10/21 → 8/10/21

Keywords

8T SRAM
In-Memory Computing
PBTI
supplemental transistor

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10.1109/DFT52944.2021.9568343

Cite this

Chang, W., Chen, Y. G., Huang, P. Y., & Li, J. F. (2021). An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. In L. Dilillo, L. Cassano, & A. Papadimitriou (Eds.), 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2021-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT52944.2021.9568343

Chang, Wei ; Chen, Yu Guang ; Huang, Po Yeh et al. / An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. editor / Luigi Dilillo ; Luca Cassano ; Athanasios Papadimitriou. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

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title = "An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing",

abstract = "In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.",

keywords = "8T SRAM, In-Memory Computing, PBTI, supplemental transistor",

author = "Wei Chang and Chen, {Yu Guang} and Huang, {Po Yeh} and Li, {Jin Fu}",

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Chang, W, Chen, YG, Huang, PY & Li, JF 2021, An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. in L Dilillo, L Cassano & A Papadimitriou (eds), 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, vol. 2021-October, Institute of Electrical and Electronics Engineers Inc., 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Virtual, Athens, Greece, 6/10/21. https://doi.org/10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. / Chang, Wei; Chen, Yu Guang; Huang, Po Yeh et al.
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. ed. / Luigi Dilillo; Luca Cassano; Athanasios Papadimitriou. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2021-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In-memory computing (IMC), which processes data directly in memory arrays through analog signal capture, provides fast and efficient Boolean logic computation. One of such a structure is SRAM-based IMC, which uses the discharge amplitude to realize various Boolean functions. However, the PVT variations as well as aging effects will seriously impact the accuracy of the IMC results. To improve the accuracy and to extend the system lifetime, in this paper we propose a novel 8T CMOS SRAM IMC structure which uses supplemental transistors to tolerance the PBTI effects on NMOS transistors. Experimental results show a significant lifetime extension with the proposed method.

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Chang W, Chen YG, Huang PY, Li JF. An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. In Dilillo L, Cassano L, Papadimitriou A, editors, 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. Institute of Electrical and Electronics Engineers Inc. 2021. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT52944.2021.9568343

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

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