This letter presents an 18 to 33 GHz fully-integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The Darlington cell with cascode topology was adopted as the power cell to elevate the maximum available gain of the transistors in standard 0.18 μm CMOS technology for being capable of operating at Ka band. Moreover, utilizing broadband and low-loss Guanella-type transmission-line transformers as the matching networks, the proposed PA exhibits a flat gain of 15.2 ± 1 dB from 17.8 to 34.6 GHz, and 3 dB bandwidths from 17 to 35.2 GHz. The 3 dB power bandwidths are from 18 to 33 GHz with saturated output power of 19.5 dBm. The output 1 dB gain compression point ( OP1dB) of 16 dBm and power-added efficiency of 10.2% are achieved at 26 GHz under a power consumption of 711 mW. The chip dimension, including the pads, is 1.41 × 0.61 mm2.
- CMOS power amplifier (PA)
- Darlington cell
- Transmission-line transformer (TLT)