All-digital PLL using pulse-based DCO

Hong Yi Huang; Jen Chieh Liu; Kuo Hsing Cheng

doi:10.1109/ICECS.2007.4511228

All-digital PLL using pulse-based DCO

Hong Yi Huang, Jen Chieh Liu, Kuo Hsing Cheng

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.18um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7ps and 44ps at 450-MHz, respectively. Power consumption is 16.2mW at 450-MHz.

Original language	English
Title of host publication	ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages	1268-1271
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2007.4511228
State	Published - 2007
Event	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco Duration: 11 Dec 2007 → 14 Dec 2007

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/Territory	Morocco
City	Marrakech
Period	11/12/07 → 14/12/07

Access to Document

10.1109/ICECS.2007.4511228

Cite this

@inproceedings{bd61d71df12144f797b047dfcca6d39e,

title = "All-digital PLL using pulse-based DCO",

abstract = "A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.18um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7ps and 44ps at 450-MHz, respectively. Power consumption is 16.2mW at 450-MHz.",

author = "Huang, {Hong Yi} and Liu, {Jen Chieh} and Cheng, {Kuo Hsing}",

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note = "14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 ; Conference date: 11-12-2007 Through 14-12-2007",

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Huang, HY, Liu, JC & Cheng, KH 2007, All-digital PLL using pulse-based DCO. in ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems., 4511228, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 1268-1271, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Morocco, 11/12/07. https://doi.org/10.1109/ICECS.2007.4511228

All-digital PLL using pulse-based DCO. / Huang, Hong Yi; Liu, Jen Chieh; Cheng, Kuo Hsing.
ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 1268-1271 4511228 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Huang, Hong Yi

AU - Liu, Jen Chieh

AU - Cheng, Kuo Hsing

PY - 2007

Y1 - 2007

N2 - A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.18um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7ps and 44ps at 450-MHz, respectively. Power consumption is 16.2mW at 450-MHz.

AB - A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.18um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7ps and 44ps at 450-MHz, respectively. Power consumption is 16.2mW at 450-MHz.

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U2 - 10.1109/ICECS.2007.4511228

DO - 10.1109/ICECS.2007.4511228

M3 - 會議論文篇章

AN - SCOPUS:50649105701

SN - 1424413788

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T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems

T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007

Y2 - 11 December 2007 through 14 December 2007

ER -

All-digital PLL using pulse-based DCO

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