All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Tzu Chi Huang; Hong Yi Huang; Jen Chieh Liu; Kuo Hsing Cheng; Ching Hsing Luo

doi:10.1109/ISCAS.2011.5937608

All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Tzu Chi Huang, Hong Yi Huang, Jen Chieh Liu, Kuo Hsing Cheng, Ching Hsing Luo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um². The power consumption is 5.4 mW at 416 MHz.

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	486-489
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937608
State	Published - 2011
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

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10.1109/ISCAS.2011.5937608

Cite this

Huang, T. C., Huang, H. Y., Liu, J. C., Cheng, K. H., & Luo, C. H. (2011). All digital phase-locked loop using active inductor oscillator and novel locking algorithm. In 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (pp. 486-489). Article 5937608 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2011.5937608

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title = "All digital phase-locked loop using active inductor oscillator and novel locking algorithm",

abstract = "A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um2. The power consumption is 5.4 mW at 416 MHz.",

author = "Huang, {Tzu Chi} and Huang, {Hong Yi} and Liu, {Jen Chieh} and Cheng, {Kuo Hsing} and Luo, {Ching Hsing}",

year = "2011",

doi = "10.1109/ISCAS.2011.5937608",

language = "???core.languages.en_GB???",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "486--489",

booktitle = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011",

note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

Huang, TC, Huang, HY, Liu, JC, Cheng, KH & Luo, CH 2011, All digital phase-locked loop using active inductor oscillator and novel locking algorithm. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937608, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 486-489, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937608

All digital phase-locked loop using active inductor oscillator and novel locking algorithm. / Huang, Tzu Chi; Huang, Hong Yi; Liu, Jen Chieh et al.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 486-489 5937608 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um2. The power consumption is 5.4 mW at 416 MHz.

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All digital phase-locked loop using active inductor oscillator and novel locking algorithm

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