Abstract
A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-μm standard complementary metal oxide semiconductor process with a core area of 0.091mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40-60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.
Original language | English |
---|---|
Article number | 04CF02 |
Journal | Japanese Journal of Applied Physics |
Volume | 56 |
Issue number | 4 |
DOIs | |
State | Published - Apr 2017 |