@inproceedings{d2c1c73dee044262b79186ed972296b2,
title = "A wide-range DLL-based clock generator with phase error calibration",
abstract = "In this paper, a wide-range operation and phase error calibration DLL-based clock generator is proposed. By using multi-band voltage controlled delay line (MBVCDL) and frequency multiplier to expand the operation frequency range of clock generator. The proposed clock generator uses detect window phase detector (DWPD) to effectively reduce phase error. The proposed DLL can reduce the maximum phase error form 3.57° to 1.098° of DLL multiphase output at 250MHz. The simulation results show that the proposed DLL operates from 25MHz to 250MHz and the frequency multiplier synthesizes frequency from 250MHz to 2.5GHz. The power dissipation and the peak-to-peak jitter are 10.1mW and 22.6ps at 2.5GHz frequency multiplier output frequency.",
author = "Cheng, {Kuo Hsing} and Su, {Chia Wei} and Wu, {Meng Jhe} and Chang, {Yu Ling}",
year = "2008",
doi = "10.1109/ICECS.2008.4674974",
language = "???core.languages.en_GB???",
isbn = "9781424421824",
series = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",
pages = "798--801",
booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",
note = "null ; Conference date: 31-08-2008 Through 03-09-2008",
}