A wide-range DLL-based clock generator with phase error calibration

Kuo Hsing Cheng, Chia Wei Su, Meng Jhe Wu, Yu Ling Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this paper, a wide-range operation and phase error calibration DLL-based clock generator is proposed. By using multi-band voltage controlled delay line (MBVCDL) and frequency multiplier to expand the operation frequency range of clock generator. The proposed clock generator uses detect window phase detector (DWPD) to effectively reduce phase error. The proposed DLL can reduce the maximum phase error form 3.57° to 1.098° of DLL multiphase output at 250MHz. The simulation results show that the proposed DLL operates from 25MHz to 250MHz and the frequency multiplier synthesizes frequency from 250MHz to 2.5GHz. The power dissipation and the peak-to-peak jitter are 10.1mW and 22.6ps at 2.5GHz frequency multiplier output frequency.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages798-801
Number of pages4
DOIs
StatePublished - 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

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