A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application

Chih Wei Tsai, Yu Ting Chiu, Yo Hao Tu, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper presents an all-digital delay-locked loop (ADDLL) with wide operating range for double data rate synchronous dynamic random access memory (DDR SDRAM) application. To avoid the quadrature phase error caused by harmonic lock, the proposed auto-calibrated edge detector (ACED) utilizes novel harmonic lock detection technique and auto-calibration technique to extend the operating range. To verify, the proposed circuit was fabricated using 90-nm standard CMOS process with a 1-V supply voltage. The core area is 0.089 mm2. The measurement result shows the operating range of proposed ADDLL is from 0.1 to 2.7 GHz with peak-to-peak period jitter less than 5 ps. The quadrature output duty-cycle error is less than 1.9%.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
StatePublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 27 May 201830 May 2018

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/TerritoryItaly
CityFlorence
Period27/05/1830/05/18

Keywords

  • all-digital delay-locked loop (ADDLL)
  • double data rate synchronous dynamic random access memory (DDR SDRAM)
  • duty cycle
  • harmonic lock
  • stuck lock

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