A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications

Chih Wei Tsai, Yu Ting Chiu, Yo Hao Tu, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)-DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 $\mu \text {m} \times 234\,\,\mu \text{m}$. The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.

Original languageEnglish
Pages (from-to)1720-1729
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume29
Issue number10
DOIs
StatePublished - 1 Oct 2021

Keywords

  • All-digital delay-locked loop (ADDLL)
  • double data rate (DDR)
  • duty cycle
  • harmonic locking
  • synchronous mirror delay (SMD)

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