A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop

Ching Chi Chang, Chien Chih Lin, Muh Tian Shiue, Chorng Kuang Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a two-fold carrier recovery loop that possesses /spl plusmn/25000-ppm pull-in range and 7-ms acquisition time for 64-QAM blind adaptive system. The carrier recovery system contains a prior wide-band loop to acquire a coarse carrier frequency and a posterior narrow-band loop to achieve -82 dBc jitter suppression. It can be applied to a 4.035-MHz low-IF cable modem system with the /spl plusmn/100-kHz frequency offset tolerance requirement. The two-fold carrier recovery loop operates in consecutive three stages, which are Costas carrier phase estimation, DDML carrier phase estimation, and DD-MMSE carrier phase estimation. The proposed architecture is hardware efficient since the three-staged operation shares most of the circuit functions.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages358-361
Number of pages4
DOIs
StatePublished - 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 6 May 20019 May 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Conference

Conference2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/TerritoryAustralia
CitySydney, NSW
Period6/05/019/05/01

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