A VLSI design of new memory reduction turbo code decoder

Tsung Han Tsai; Cheng Hung Lin

A VLSI design of new memory reduction turbo code decoder

Tsung Han Tsai, Cheng Hung Lin

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm², clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.

Original language	English
Pages	249-252
Number of pages	4
State	Published - 2005
Event	9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA - Hsinchu, Taiwan Duration: 28 May 2005 → 30 May 2005

Conference

Conference	9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA
Country/Territory	Taiwan
City	Hsinchu
Period	28/05/05 → 30/05/05

Cite this

@conference{ee928dadcecc428280992c798f7c7d4c,

title = "A VLSI design of new memory reduction turbo code decoder",

abstract = "In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm2, clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.",

author = "Tsai, {Tsung Han} and Lin, {Cheng Hung}",

year = "2005",

language = "???core.languages.en_GB???",

pages = "249--252",

note = "9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA ; Conference date: 28-05-2005 Through 30-05-2005",

}

TY - CONF

T1 - A VLSI design of new memory reduction turbo code decoder

AU - Tsai, Tsung Han

AU - Lin, Cheng Hung

PY - 2005

Y1 - 2005

N2 - In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm2, clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.

AB - In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04×3.04mm2, clock frequency 145 MHz in UMC 0.18um 1p6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.

UR - http://www.scopus.com/inward/record.url?scp=27144555291&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:27144555291

SP - 249

EP - 252

T2 - 9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA

Y2 - 28 May 2005 through 30 May 2005

ER -

A VLSI design of new memory reduction turbo code decoder

Abstract

Conference

Fingerprint

Cite this