A vlsi architecture design for dual-mode qam and vsb digital catv transceiver

Keyphrases

• Dual-mode 100%
• VLSI Architecture 100%
• Transceiver 100%
• Proposed Architecture 100%
• Architectural Design 100%
• Carrier Recovery 100%
• Blind Equalization 100%
• Fractionally Spaced 100%
• All-digital 50%
• Finite Length 50%
• Carrier Frequency Offset 50%
• Modem 50%
• Input Signals 50%
• Carrier Frequency 50%
• Timing Recovery 50%
• Symbol Rate 50%
• 64QAM 50%
• Digital AGC 50%
• Symbol Timing Recovery 50%
• 8-VSB 50%
• Rate Offset 50%
• Digital Demodulator 50%
• High-speed Digital Signal 50%

Engineering

• Equalizers 100%
• Transceiver 100%
• Decision Feedback Equalizers 100%
• Carrier Frequency 100%
• Simulation Result 50%
• Symbol Rate 50%
• Demodulator 50%
• Input Signal 50%