A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

Yen Liang Yeh, Xiang Lin, Hong Yeh Chang, Kevin Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Fingerprint

Dive into the research topics of 'A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider'. Together they form a unique fingerprint.

Physics & Astronomy

Engineering & Materials Science