A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

Yen Liang Yeh, Xiang Lin, Hong Yeh Chang, Kevin Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.

Original languageEnglish
Title of host publicationRFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509012350
DOIs
StatePublished - 27 Sep 2016
Event2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan
Duration: 24 Aug 201626 Aug 2016

Publication series

NameRFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

Conference

Conference2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Country/TerritoryTaiwan
CityTaipei
Period24/08/1626/08/16

Keywords

  • CMOS
  • injection-locked frequency divider (ILFD)
  • millimeter-wave (MMW)
  • phase-locked loop (PLL)

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