A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

Yen Liang Yeh; Xiang Lin; Hong Yeh Chang; Kevin Chen

doi:10.1109/RFIT.2016.7578116

A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

Yen Liang Yeh, Xiang Lin, Hong Yeh Chang, Kevin Chen

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.

Original language	English
Title of host publication	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509012350
DOIs	https://doi.org/10.1109/RFIT.2016.7578116
State	Published - 27 Sep 2016
Event	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan Duration: 24 Aug 2016 → 26 Aug 2016

Publication series

Name	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

Conference

Conference	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Country/Territory	Taiwan
City	Taipei
Period	24/08/16 → 26/08/16

Keywords

CMOS
injection-locked frequency divider (ILFD)
millimeter-wave (MMW)
phase-locked loop (PLL)

Access to Document

10.1109/RFIT.2016.7578116

Cite this

Yeh, Y. L., Lin, X., Chang, H. Y., & Chen, K. (2016). A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider. In RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology Article 7578116 (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2016.7578116

Yeh, Yen Liang ; Lin, Xiang ; Chang, Hong Yeh et al. / A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider. RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology).

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abstract = "A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.",

keywords = "CMOS, injection-locked frequency divider (ILFD), millimeter-wave (MMW), phase-locked loop (PLL)",

author = "Yeh, {Yen Liang} and Xiang Lin and Chang, {Hong Yeh} and Kevin Chen",

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Yeh, YL, Lin, X, Chang, HY & Chen, K 2016, A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider. in RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology., 7578116, RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016, Taipei, Taiwan, 24/08/16. https://doi.org/10.1109/RFIT.2016.7578116

A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider. / Yeh, Yen Liang; Lin, Xiang; Chang, Hong Yeh et al.
RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. 7578116 (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chang, Hong Yeh

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PY - 2016/9/27

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N2 - A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.

AB - A K-band 65 nm CMOS low dc power low phase noise phase-locked loop (PLL) using divide-by-three injection-locked frequency divider (ILFD) is presented in this paper. Based on the injection-locked technique for the first stage of the frequency divider chain, the proposed PLL can be operated up to K-band with low dc power consumption. The ILFD features high division, high speed, and low power. With a total dc power consumption of 43.4 mW, the proposed PLL demonstrates a phase noise of -83.5 dBc/Hz at 1 MHz offset, a reference spur suppression of -66 dBc, and a maximum operation frequency of up to 58.9 GHz. This work can be compared to the reported advanced K-band CMOS PLLs and suitable for the local oscillator chain of the millimeter-wave frontends.

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Yeh YL, Lin X, Chang HY, Chen K. A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider. In RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc. 2016. 7578116. (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology). doi: 10.1109/RFIT.2016.7578116

A V-band 65 nm CMOS low DC power low phase noise PLL using divide-by-three injection-locked frequency divider

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