A two-phase fault simulation scheme for sequential circuits

Wen Ching Wu, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalArticlepeer-review

Abstract

A two-phase fault simulation scheme for sequential circuits is proposed. In this fault simulation, the input sequence is divided into two parts. In the first phase, fault free simulation is performed with the first sequence of patterns. In the second phase, fault simulation is performed with the rest of the patterns. Five cases of faults which result from two-phase fault simulation are discussed in detail. Significant speedup in simulation time can be obtained because this fault simulation approach can quickly drop Case 1 faults, which are time-consuming faults and would be considered undetectable in the traditional three-value fault simulation but are actually detected in exact fault simulation. Almost "exact" results can be obtained for detected faults except for a small percentage of over-detected-faults (ODFs) and under-detected-faults (UDFs).

Original languageEnglish
Pages (from-to)669-686
Number of pages18
JournalJournal of Information Science and Engineering
Volume14
Issue number3
StatePublished - Sep 1998

Keywords

  • Computer-aided-design
  • Digital testing
  • Fault simulation
  • Sequential circuits
  • Untestable faults

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