A two-phase fault simulation scheme for sequential circuits

W. C. Wu, C. L. Lee, J. E. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A two-phase fault simulation scheme for sequential circuits is proposed. The scheme is done by first performing the true value simulation with several initial patterns and then by performing the fault simulation with the rest of patterns. With the fault simulation approach, some faults which consume much simulation time can be easily and quickly identified and dropped early. As a result, significant speedup on simulation time is obtained. Five cases of faults which cause problems in fault simulation are also discussed.

Original languageEnglish
Title of host publicationATS 1993 Proceedings - 2nd Asian Test Symposium
PublisherIEEE Computer Society
Pages60-65
Number of pages6
ISBN (Electronic)081863930X
DOIs
StatePublished - 1993
Event2nd IEEE Asian Test Symposium, ATS 1993 - Beijing, China
Duration: 16 Nov 199318 Nov 1993

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference2nd IEEE Asian Test Symposium, ATS 1993
Country/TerritoryChina
CityBeijing
Period16/11/9318/11/93

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