Three-dimensional (3-D) integration technology using through-silicon via (TSV) is an emerging integrated-circuit (IC) design technology. In this paper, we propose a repair scheme to enhance the yield of TSVs in 3-D ICs. The proposed TSV repair scheme uses an enhanced test access architecture to alleviate the requirement of additional repair registers such that the area cost can be drastically reduced. In comparison with existing scanbased test and repair approaches, simulation and analysis results show that the proposed TSV repair scheme can provide the best final yield and consume the smallest area cost for 128 TSVs with one spare TSV. On the other hand, the proposed repair schemes with 1149.1-based and 1500-based wrapper cells for 128 TSVs only need 12% and 20% additional area cost in comparison with the 1149.1 and 1500 test access architectures.