A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Kuo Hsing Cheng, Chang Chien Hu, Jen Chieh Liu, Hong Yi Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

Original languageEnglish
Title of host publicationProceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Pages285-288
Number of pages4
DOIs
StatePublished - 2010
Event13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 - Vienna, Austria
Duration: 14 Apr 201016 Apr 2010

Publication series

NameProceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Conference

Conference13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Country/TerritoryAustria
CityVienna
Period14/04/1016/04/10

Keywords

  • All digital PLL (ADPLL)
  • Digital controlled oscillator (DCO)
  • Multi-phase
  • Time-to-digital (TDC)

Fingerprint

Dive into the research topics of 'A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop'. Together they form a unique fingerprint.

Cite this