A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Kuo Hsing Cheng; Chang Chien Hu; Jen Chieh Liu; Hong Yi Huang

doi:10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

Kuo Hsing Cheng, Chang Chien Hu, Jen Chieh Liu, Hong Yi Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

Original language	English
Title of host publication	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Pages	285-288
Number of pages	4
DOIs	https://doi.org/10.1109/DDECS.2010.5491766
State	Published - 2010
Event	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 - Vienna, Austria Duration: 14 Apr 2010 → 16 Apr 2010

Publication series

Name	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Conference

Conference	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
Country/Territory	Austria
City	Vienna
Period	14/04/10 → 16/04/10

Keywords

All digital PLL (ADPLL)
Digital controlled oscillator (DCO)
Multi-phase
Time-to-digital (TDC)

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10.1109/DDECS.2010.5491766

Cite this

Cheng, K. H., Hu, C. C., Liu, J. C., & Huang, H. Y. (2010). A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. In Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 (pp. 285-288). Article 5491766 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). https://doi.org/10.1109/DDECS.2010.5491766

Cheng, Kuo Hsing ; Hu, Chang Chien ; Liu, Jen Chieh et al. / A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. pp. 285-288 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

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title = "A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop",

abstract = "This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.",

keywords = "All digital PLL (ADPLL), Digital controlled oscillator (DCO), Multi-phase, Time-to-digital (TDC)",

author = "Cheng, {Kuo Hsing} and Hu, {Chang Chien} and Liu, {Jen Chieh} and Huang, {Hong Yi}",

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booktitle = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",

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Cheng, KH, Hu, CC, Liu, JC & Huang, HY 2010, A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. in Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010., 5491766, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, pp. 285-288, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, 14/04/10. https://doi.org/10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. / Cheng, Kuo Hsing; Hu, Chang Chien; Liu, Jen Chieh et al.
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 285-288 5491766 (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

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Cheng KH, Hu CC, Liu JC, Huang HY. A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. In Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. 2010. p. 285-288. 5491766. (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010). doi: 10.1109/DDECS.2010.5491766

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

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