A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

Yo Hao Tu; Kuo Hsing Cheng; Yian An Lin; Hong Yi Huang

doi:10.1109/DDECS.2015.29

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

Yo Hao Tu, Kuo Hsing Cheng, Yian An Lin, Hong Yi Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
Editors	Heinrich Theodor Vierhaus, Zoran Stamenkovic, Witold Pleskacz, Jaan Raik
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	79-82
Number of pages	4
ISBN (Electronic)	9781479967803
DOIs	https://doi.org/10.1109/DDECS.2015.29
State	Published - 13 Aug 2015
Event	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015 - Belgrade, Serbia Duration: 22 Apr 2015 → 24 Apr 2015

Publication series

Name	Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015

Conference

Conference	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
Country/Territory	Serbia
City	Belgrade
Period	22/04/15 → 24/04/15

Keywords

synchronization circuit
synchronous mirror delay (SMD) and duty-cycle tuneable technology

Access to Document

10.1109/DDECS.2015.29

Cite this

Tu, Y. H., Cheng, K. H., Lin, Y. A., & Huang, H. Y. (2015). A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. In H. T. Vierhaus, Z. Stamenkovic, W. Pleskacz, & J. Raik (Eds.), Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015 (pp. 79-82). Article 7195672 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2015.29

Tu, Yo Hao ; Cheng, Kuo Hsing ; Lin, Yian An et al. / A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. editor / Heinrich Theodor Vierhaus ; Zoran Stamenkovic ; Witold Pleskacz ; Jaan Raik. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 79-82 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

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abstract = "This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.",

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Tu, YH, Cheng, KH, Lin, YA & Huang, HY 2015, A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. in HT Vierhaus, Z Stamenkovic, W Pleskacz & J Raik (eds), Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015., 7195672, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 79-82, 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015, Belgrade, Serbia, 22/04/15. https://doi.org/10.1109/DDECS.2015.29

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. / Tu, Yo Hao; Cheng, Kuo Hsing; Lin, Yian An et al.
Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. ed. / Heinrich Theodor Vierhaus; Zoran Stamenkovic; Witold Pleskacz; Jaan Raik. Institute of Electrical and Electronics Engineers Inc., 2015. p. 79-82 7195672 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.

AB - This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.

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Tu YH, Cheng KH, Lin YA, Huang HY. A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. In Vierhaus HT, Stamenkovic Z, Pleskacz W, Raik J, editors, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 79-82. 7195672. (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015). doi: 10.1109/DDECS.2015.29

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

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