In this paper, a low-power high-speed static frequency divider is proposed. By utilizing the forward body-bias (FBB) technique and parallel switching topology which employ differential PMOS input pair, the proposed 2:1 static frequency divider can not only be operated at a supply voltage of 0.7V but also keep the structure of tail current source to provide constant current. The frequency divider is designed based on TSMC 0.18μm 1p6m CMOS process. The 2:1 frequency divider can be operated up to maximum operating frequency 10.18 GHz while consuming 1.68 mW from a supply voltage of 0.9V. As operating at supply voltage of 0.7V, the operating frequency is 4.07GHz and the power dissipation is 0.96mW.
|Number of pages
|Proceedings - IEEE International Symposium on Circuits and Systems
|Published - 2007
|2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 2007 → 30 May 2007