A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Rei Fu Huang, Jin Fu Li, Jen Chieh Yeh, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order improving the accuracy of the analysis results.

Original languageEnglish
Title of host publicationProceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages262-267
Number of pages6
ISBN (Electronic)0769516416, 9780769516417
DOIs
StatePublished - 2002
Event8th IEEE International On-Line Testing Workshop, IOLTW 2002 - Isle of Bendor, France
Duration: 8 Jul 200210 Jul 2002

Publication series

NameProceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Conference

Conference8th IEEE International On-Line Testing Workshop, IOLTW 2002
Country/TerritoryFrance
CityIsle of Bendor
Period8/07/0210/07/02

Keywords

  • embedded memory
  • memory repair
  • memory testing
  • redundancy analysis
  • simulation

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