@inproceedings{890f98ff0a7846729387077f7dcf6632,
title = "A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs",
abstract = "Embedded memories currently constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper proposes a shared parallel BISR scheme for random access memories (RAMs) in SOCs. The shared parallel BISR can test and repair multiple RAMs simultaneously. A global timemultiplexed built-in redundancy analyzer (TM-BIRA) is used to allocate redundancies of the RAMs under test and repair.We als design a 1500-compatible wrapper for chip-level control of the shared parallel BISR circuits. In comparison with the dedicated parallel BISR scheme (each memory has a self-contained BISR circuit), the proposed parallel BISR scheme can achieve 20% reduction of area cost by paying additional 0.005% test and repair time for serving 5 RAMs with spare rows and spare columns.",
author = "Tseng, {Tsu Wei} and Li, {Jin Fu}",
year = "2008",
doi = "10.1109/TEST.2008.4700617",
language = "???core.languages.en_GB???",
isbn = "9781424424030",
series = "Proceedings - International Test Conference",
booktitle = "Proceedings - International Test Conference 2008, ITC 2008",
note = "International Test Conference 2008, ITC 2008 ; Conference date: 28-10-2008 Through 30-10-2008",
}