A scan matrix design for low power scan-based test

Shih Ping Lin, Chung Len Lee, Jwu E. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the junction mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.

Original languageEnglish
Title of host publicationProceedings - 14th Asian Test Symposium, ATS 2005
Number of pages6
StatePublished - 2005
Event14th Asian Test Symposium, ATS 2005 - Calcutta, India
Duration: 18 Dec 200521 Dec 2005

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference14th Asian Test Symposium, ATS 2005


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