A scalable parallel hardware architecture for connected component labeling

Chung Yuan Lin, Sz Yan Li, Tsung Han Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

The parallel connected component labeling used in binary image analysis is reconsidered in this paper for the high throughput and intermediate memory requirements problem on high dimensional image sequence. It is based on a proposed dual-parallel connected component labeling method. The main idea is to break the sequentiality of the labeling procedure by separating image into slices and to correctly delimit the extent of all connected components locally, on each slice, simultaneously. According to the proposed method, a scalable architecture which can be adaptive to different throughput requirement is derived. The proposed architecture consists of local label assignment, local label fusion, and global process unit. The forest structure is introduced to cope with both global and local label equivalent. Based on the forest structure, find and union operations are implemented to complete the entire connected components labeling during two raster scans. Performance of the proposed architecture estimated in terms of the number of clocks and memory requirement are brought forward to justify the superiority of the novel design compared against previous implementation.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Image Processing, ICIP 2010 - Proceedings
Pages3753-3756
Number of pages4
DOIs
StatePublished - 2010
Event2010 17th IEEE International Conference on Image Processing, ICIP 2010 - Hong Kong, Hong Kong
Duration: 26 Sep 201029 Sep 2010

Publication series

NameProceedings - International Conference on Image Processing, ICIP
ISSN (Print)1522-4880

Conference

Conference2010 17th IEEE International Conference on Image Processing, ICIP 2010
Country/TerritoryHong Kong
CityHong Kong
Period26/09/1029/09/10

Keywords

  • Connected component
  • Labeling algorithm
  • Real-time
  • Scalable architecture

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