A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs

Tsu Wei Tseng, Jin Fu Li, Chih Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

29 Scopus citations

Abstract

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512×4×256 design parameters and four memory instances (64×2×32, 128×2×64, 256×4×128, and 512×4×256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512×4×256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%.

Original languageEnglish
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
DOIs
StatePublished - 2006
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: 22 Oct 200627 Oct 2006

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

Conference2006 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA
Period22/10/0627/10/06

Keywords

  • Built-in redundancy-analysis
  • Built-in self-repair
  • March test
  • RAMs
  • Reconfigurable
  • Redundancy
  • SOCs

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