A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions

Yu Guang Chen; Hung Yi Chiang; Chi Wei Hsu; Tsung Han Hsieh; Jing Yang Jou

doi:10.1109/ISOCC53507.2021.9613976

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions

Yu Guang Chen, Hung Yi Chiang, Chi Wei Hsu, Tsung Han Hsieh, Jing Yang Jou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Convolutional Neural Networks (CNNs) are widely applied in various computer version applications such as object recognition and image classification. With large amount of Multiply Accumulate Operations (MACs) in CNN computations, it is a trend to process the data locally at edge devices to avoid significant data movement. MobileNets were proposed as a light-weight neural network for mobile and embedded devices by using depthwise separable convolutions. Moreover, to further reduce commutation efforts, quantization can be appropriately applied to MobileNets without significant accuracy loss. To provide an efficient computation platform for quantized MobileNets, in this paper we propose a novel performance-Aware reconfigurable accelerator design which prefect fit the depthwise separable convolutions. Experimental results show that we can achieve 16% area reduction and 1.07x speedup compared to previous MobileNets accelerator design.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	290-291
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613976
State	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	6/10/21 → 9/10/21

Keywords

AI accelerator
Mobilenets
Reconfigurable Structure

Access to Document

10.1109/ISOCC53507.2021.9613976

考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(3/3)
Jou, J.-Y. (PI)
1/08/23 → 31/07/24
Project: Research
Machine Learning Based Negative-Bias Temperature Instability (Nbti) Detection and Mitigation for Heterogeneous Multi-Core Systems(1/2)
Chen, Y.-G. (PI)
1/08/20 → 31/07/21
Project: Research

Cite this

Chen, Y. G., Chiang, H. Y., Hsu, C. W., Hsieh, T. H., & Jou, J. Y. (2021). A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 290-291). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613976

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title = "A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions",

abstract = "Convolutional Neural Networks (CNNs) are widely applied in various computer version applications such as object recognition and image classification. With large amount of Multiply Accumulate Operations (MACs) in CNN computations, it is a trend to process the data locally at edge devices to avoid significant data movement. MobileNets were proposed as a light-weight neural network for mobile and embedded devices by using depthwise separable convolutions. Moreover, to further reduce commutation efforts, quantization can be appropriately applied to MobileNets without significant accuracy loss. To provide an efficient computation platform for quantized MobileNets, in this paper we propose a novel performance-Aware reconfigurable accelerator design which prefect fit the depthwise separable convolutions. Experimental results show that we can achieve 16% area reduction and 1.07x speedup compared to previous MobileNets accelerator design.",

keywords = "AI accelerator, Mobilenets, Reconfigurable Structure",

author = "Chen, {Yu Guang} and Chiang, {Hung Yi} and Hsu, {Chi Wei} and Hsieh, {Tsung Han} and Jou, {Jing Yang}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

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Chen, YG, Chiang, HY, Hsu, CW, Hsieh, TH & Jou, JY 2021, A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 290-291, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613976

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. / Chen, Yu Guang; Chiang, Hung Yi; Hsu, Chi Wei et al.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 290-291 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions

AU - Chen, Yu Guang

AU - Chiang, Hung Yi

AU - Hsu, Chi Wei

AU - Hsieh, Tsung Han

AU - Jou, Jing Yang

PY - 2021

Y1 - 2021

N2 - Convolutional Neural Networks (CNNs) are widely applied in various computer version applications such as object recognition and image classification. With large amount of Multiply Accumulate Operations (MACs) in CNN computations, it is a trend to process the data locally at edge devices to avoid significant data movement. MobileNets were proposed as a light-weight neural network for mobile and embedded devices by using depthwise separable convolutions. Moreover, to further reduce commutation efforts, quantization can be appropriately applied to MobileNets without significant accuracy loss. To provide an efficient computation platform for quantized MobileNets, in this paper we propose a novel performance-Aware reconfigurable accelerator design which prefect fit the depthwise separable convolutions. Experimental results show that we can achieve 16% area reduction and 1.07x speedup compared to previous MobileNets accelerator design.

AB - Convolutional Neural Networks (CNNs) are widely applied in various computer version applications such as object recognition and image classification. With large amount of Multiply Accumulate Operations (MACs) in CNN computations, it is a trend to process the data locally at edge devices to avoid significant data movement. MobileNets were proposed as a light-weight neural network for mobile and embedded devices by using depthwise separable convolutions. Moreover, to further reduce commutation efforts, quantization can be appropriately applied to MobileNets without significant accuracy loss. To provide an efficient computation platform for quantized MobileNets, in this paper we propose a novel performance-Aware reconfigurable accelerator design which prefect fit the depthwise separable convolutions. Experimental results show that we can achieve 16% area reduction and 1.07x speedup compared to previous MobileNets accelerator design.

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KW - Reconfigurable Structure

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Chen YG, Chiang HY, Hsu CW, Hsieh TH, Jou JY. A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 290-291. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613976

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions

Abstract

Publication series

Conference

Keywords

Access to Document

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Projects

考量老化且適用於邊緣運算之深度類神經網路加速器設計與優化研究(3/3)

Machine Learning Based Negative-Bias Temperature Instability (Nbti) Detection and Mitigation for Heterogeneous Multi-Core Systems(1/2)

Cite this