A read-write aware DRAM scheduling for power reduction in multi-core systems

Keyphrases

• Power Reduction 100%
• Multicore Systems 100%
• DRAM Scheduling 100%
• High Performance 50%
• Performance Degradation 50%
• Power Consumption 50%
• Low Power 50%
• Power Efficiency 50%
• Multicore Architecture 50%
• DRAM Power 50%

Computer Science

• Multicore System 100%
• Power Consumption 50%
• Performance Degradation 50%
• Power Efficiency 50%
• Multi-Core Architectures 50%

Engineering

• Electric Power Utilization 100%
• Performance Degradation 100%