A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai, Gung Yu Pan, Hsien Kai Kuo, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

Original languageEnglish
Title of host publication2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages604-609
Number of pages6
DOIs
StatePublished - 2014
Event2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
Duration: 20 Jan 201423 Jan 2014

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Country/TerritorySingapore
CitySuntec
Period20/01/1423/01/14

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