A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai; Gung Yu Pan; Hsien Kai Kuo; Jing Yang Jou

doi:10.1109/ASPDAC.2014.6742957

A read-write aware DRAM scheduling for power reduction in multi-core systems

Chih Yen Lai, Gung Yu Pan, Hsien Kai Kuo, Jing Yang Jou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

Original language	English
Title of host publication	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages	604-609
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2014.6742957
State	Published - 2014
Event	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore Duration: 20 Jan 2014 → 23 Jan 2014

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Country/Territory	Singapore
City	Suntec
Period	20/01/14 → 23/01/14

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10.1109/ASPDAC.2014.6742957

Cite this

Lai, C. Y., Pan, G. Y., Kuo, H. K., & Jou, J. Y. (2014). A read-write aware DRAM scheduling for power reduction in multi-core systems. In 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings (pp. 604-609). Article 6742957 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2014.6742957

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title = "A read-write aware DRAM scheduling for power reduction in multi-core systems",

abstract = "The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.",

author = "Lai, {Chih Yen} and Pan, {Gung Yu} and Kuo, {Hsien Kai} and Jou, {Jing Yang}",

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Lai, CY, Pan, GY, Kuo, HK & Jou, JY 2014, A read-write aware DRAM scheduling for power reduction in multi-core systems. in 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings., 6742957, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 604-609, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, Singapore, 20/01/14. https://doi.org/10.1109/ASPDAC.2014.6742957

A read-write aware DRAM scheduling for power reduction in multi-core systems. / Lai, Chih Yen; Pan, Gung Yu; Kuo, Hsien Kai et al.
2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. 2014. p. 604-609 6742957 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.

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A read-write aware DRAM scheduling for power reduction in multi-core systems

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