A programmable online/off-line built-in self-test scheme for RAMs with ECC

Hsing Chen Lu, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low - only about 2.6% for a 4Kx39-bit SRAM.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1997-2000
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 24 May 200927 May 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/TerritoryTaiwan
CityTaipei
Period24/05/0927/05/09

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