A programmable application-specific VLSI architecture for speech recognition

Jia Ching Wang, Jhing Fa Wang, An Nan Suen, Yu Sheng Weng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we present the efficient VLSI architecture for the stand-alone application of the speech recognition system. With the analysis of the computation complexity, mel frequency cepstrum extraction and Bayesian neural network operations are the most time consuming computation tasks in the recognition algorithm. The specific recognition core to deal with them is proposed based on much algorithm improvement. The construction of the special logarithm look-up table saves the computation time and drastically reduces the memory size. Moreover, the cost efficient programmable architecture is designed for other non computation-intensive operations. The best aspects of both programmable and application specific architectures including the performance, design complexity, and flexibility are incorporated in the proposed VLSI speech recognizer.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages477-480
Number of pages4
StatePublished - 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2 Sep 20015 Sep 2001

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Conference

Conference8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/TerritoryMalta
Period2/09/015/09/01

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