It is more complicated for high speed clock and data recovery (CDR) to achieve low bit error rate (BER). It requires the high speed and resolution interpolator with regard to phase interpolator (PI) type CDR. The proposed architecture provides a low voltage, especially for sub-1V and high speed with higher power efficiency, and applies for CDR in PCI-EXPRESS II. Compared to the conventional architecture, the phase error has been improved 55.5%, the frequency has upgraded 21%, and eventually the power efficiency of proposed work has been enhanced 30%. Therefore, the high resolutions of phase interpolator in the proposed architecture would be suitable for CDR.