A novel power-on reset circuit without capacitor

Kuo Hsing Cheng, Yu Lung Lo, Wei Bin Yang

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


The power-on reset (FOR) circuit relates to the enhancement of an initializing circuit which decides the operating state of this internal circuit to be predetermined initial state uniquely, in order to prevent the malfunctioning of internal circuit of a semiconductor integrated circuit to a power-up period. In this paper, a novel power-on reset circuit is proposed. The experimental results show that the proposed circuit can generate a pulse correctly without a capacitance load even the rise time of power supply voltage is large and provides robust power supply voltage glitch immunity. Further, the delay generation portion is different from the conventional resistor-capacitor (RC) delay circuit and therefore reduces the area of the circuit.

Original languageEnglish
Title of host publicationRecent Advances in Circuits, Systems and Signal Processing
PublisherWorld Scientific and Engineering Academy and Society
Number of pages3
ISBN (Print)9608052645
StatePublished - 2002


  • Charge Clamp
  • Diode-connected
  • Power on Reset (POR)
  • Power On Reset Pulse Generator (POR-PG)
  • Power supply voltage slew rate
  • RC delay circuit


Dive into the research topics of 'A novel power-on reset circuit without capacitor'. Together they form a unique fingerprint.

Cite this