A novel power-on reset circuit without capacitor

The power-on reset (FOR) circuit relates to the enhancement of an initializing circuit which decides the operating state of this internal circuit to be predetermined initial state uniquely, in order to prevent the malfunctioning of internal circuit of a semiconductor integrated circuit to a power-up period. In this paper, a novel power-on reset circuit is proposed. The experimental results show that the proposed circuit can generate a pulse correctly without a capacitance load even the rise time of power supply voltage is large and provides robust power supply voltage glitch immunity. Further, the delay generation portion is different from the conventional resistor-capacitor (RC) delay circuit and therefore reduces the area of the circuit.