A novel efficient VLSI architecture of 2-d discrete wavelet transform

Chin Fa Hsieh; Tsung Han Tsai; Chih Hung Lai; Tai An Shan

doi:10.1109/IIH-MSP.2008.275

A novel efficient VLSI architecture of 2-d discrete wavelet transform

Chin Fa Hsieh, Tsung Han Tsai, Chih Hung Lai, Tai An Shan

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.

Original language	English
Title of host publication	Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008
Pages	647-650
Number of pages	4
DOIs	https://doi.org/10.1109/IIH-MSP.2008.275
State	Published - 2008
Event	2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008 - Harbin, China Duration: 15 Aug 2008 → 17 Aug 2008

Publication series

Name	Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008

Conference

Conference	2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008
Country/Territory	China
City	Harbin
Period	15/08/08 → 17/08/08

Keywords

Discrete wavelet transform
Lifting

Access to Document

10.1109/IIH-MSP.2008.275

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Hsieh, C. F., Tsai, T. H., Lai, C. H., & Shan, T. A. (2008). A novel efficient VLSI architecture of 2-d discrete wavelet transform. In Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008 (pp. 647-650). Article 4604139 (Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008). https://doi.org/10.1109/IIH-MSP.2008.275

Hsieh, Chin Fa ; Tsai, Tsung Han ; Lai, Chih Hung et al. / A novel efficient VLSI architecture of 2-d discrete wavelet transform. Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008. 2008. pp. 647-650 (Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008).

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abstract = "In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.",

keywords = "Discrete wavelet transform, Lifting",

author = "Hsieh, {Chin Fa} and Tsai, {Tsung Han} and Lai, {Chih Hung} and Shan, {Tai An}",

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doi = "10.1109/IIH-MSP.2008.275",

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booktitle = "Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008",

note = "2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008 ; Conference date: 15-08-2008 Through 17-08-2008",

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Hsieh, CF, Tsai, TH, Lai, CH & Shan, TA 2008, A novel efficient VLSI architecture of 2-d discrete wavelet transform. in Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008., 4604139, Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008, pp. 647-650, 2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008, Harbin, China, 15/08/08. https://doi.org/10.1109/IIH-MSP.2008.275

A novel efficient VLSI architecture of 2-d discrete wavelet transform. / Hsieh, Chin Fa; Tsai, Tsung Han; Lai, Chih Hung et al.
Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008. 2008. p. 647-650 4604139 (Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lai, Chih Hung

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AB - In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.

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KW - Lifting

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Hsieh CF, Tsai TH, Lai CH, Shan TA. A novel efficient VLSI architecture of 2-d discrete wavelet transform. In Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008. 2008. p. 647-650. 4604139. (Proceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008). doi: 10.1109/IIH-MSP.2008.275

A novel efficient VLSI architecture of 2-d discrete wavelet transform

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