A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes

Chin Fa Hsieh; Tsung Han Tsai; Neng Jye Hsu; Chih Hung Lai

doi:10.2991/jcis.2006.20

A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes

Chin Fa Hsieh, Tsung Han Tsai, Neng Jye Hsu, Chih Hung Lai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.

Original language	English
Title of host publication	Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006
DOIs	https://doi.org/10.2991/jcis.2006.20
State	Published - 2006
Event	9th Joint Conference on Information Sciences, JCIS 2006 - Taiwan, ROC, Taiwan Duration: 8 Oct 2006 → 11 Oct 2006

Publication series

Name	Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006
Volume	2006

Conference

Conference	9th Joint Conference on Information Sciences, JCIS 2006
Country/Territory	Taiwan
City	Taiwan, ROC
Period	8/10/06 → 11/10/06

Keywords

Discrete wavelet transform
Lifting

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10.2991/jcis.2006.20

Cite this

Hsieh, C. F., Tsai, T. H., Hsu, N. J., & Lai, C. H. (2006). A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes. In Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006 Article CVPRIP-75 (Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006; Vol. 2006). https://doi.org/10.2991/jcis.2006.20

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title = "A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes",

abstract = "In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.",

keywords = "Discrete wavelet transform, Lifting",

author = "Hsieh, {Chin Fa} and Tsai, {Tsung Han} and Hsu, {Neng Jye} and Lai, {Chih Hung}",

year = "2006",

doi = "10.2991/jcis.2006.20",

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isbn = "9078677015",

series = "Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006",

booktitle = "Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006",

note = "9th Joint Conference on Information Sciences, JCIS 2006 ; Conference date: 08-10-2006 Through 11-10-2006",

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Hsieh, CF, Tsai, TH, Hsu, NJ & Lai, CH 2006, A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes. in Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006., CVPRIP-75, Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006, vol. 2006, 9th Joint Conference on Information Sciences, JCIS 2006, Taiwan, ROC, Taiwan, 8/10/06. https://doi.org/10.2991/jcis.2006.20

A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes. / Hsieh, Chin Fa; Tsai, Tsung Han; Hsu, Neng Jye et al.
Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006. 2006. CVPRIP-75 (Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.

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BT - Proceedings of the 9th Joint Conference on Information Sciences, JCIS 2006

T2 - 9th Joint Conference on Information Sciences, JCIS 2006

Y2 - 8 October 2006 through 11 October 2006

ER -

A novel, efficient architecture for the ID, lifting-based DWT with folded and pipelined schemes

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Keywords

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