A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance

E. R. Hsieh, H. Y. Chang, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, Osbert Cheng, S. Simon Wong

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

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