A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance

E. R. Hsieh; H. Y. Chang; Steve S. Chung; T. P. Chen; S. A. Huang; T. J. Chen; Osbert Cheng; S. Simon Wong

doi:10.23919/VLSIT.2019.8776488

A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance

E. R. Hsieh, H. Y. Chang, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, Osbert Cheng, S. Simon Wong

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (> 10¹²), much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's V_th to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.

Original language	English
Title of host publication	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T138-T139
ISBN (Electronic)	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776488
State	Published - Jun 2019
Event	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2019-June
ISSN (Print)	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Access to Document

10.23919/VLSIT.2019.8776488

Cite this

Hsieh, E. R., Chang, H. Y., Chung, S. S., Chen, T. P., Huang, S. A., Chen, T. J., Cheng, O., & Wong, S. S. (2019). A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T138-T139). Article 8776488 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776488

Hsieh, E. R. ; Chang, H. Y. ; Chung, Steve S. et al. / A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance. 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. T138-T139 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (> 1012), much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's Vth to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.",

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Hsieh, ER, Chang, HY, Chung, SS, Chen, TP, Huang, SA, Chen, TJ, Cheng, O & Wong, SS 2019, A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776488, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T138-T139, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776488

A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance. / Hsieh, E. R.; Chang, H. Y.; Chung, Steve S. et al.
2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T138-T139 8776488 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Hsieh ER, Chang HY, Chung SS, Chen TP, Huang SA, Chen TJ et al. A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10¹² Endurance. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T138-T139. 8776488. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2019.8776488