A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

Kuo Hsing Cheng, Yu Jung Chen

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed. The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block. A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL is designed and implement by TSMC's 0-35um IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz.

Original languageEnglish
Pages (from-to)139-143
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 2001

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