A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices

E. R. Hsieh, Y. D. Wang, Steve S. Chung, J. C. Ke, C. W. Yang, S. Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The interfacial dipole and bulk trap in HKMG stack have been found to be significant to the work function variation (σVWF), in addition to the metal grains. In order to differentiate their effects on σVWF, a new variation plot is proposed and the dipole and trap effects can be distinguished. Here, we propose a simple experimental method to separate the effects of MG/HK and HK/IL interfacial dipoles. In pMOSFET, HK/IL dipoles dominate HK induced variation; MG/HK dipoles are dominant in nMOSFET. However, in terms of the reliability test, after PBTI stress, HK bulk traps play a major role in the variation of nMOSFET, while after NBTI, HK/IL dipoles are strengthened by hydrogen bonds and still dominant in work function variation of pMOSFET. Design guideline is provided to deal with the passivation of high-k traps by nitrogen concentration and the improvement of variability in HKMG CMOS devices.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006373
DOIs
StatePublished - 21 Sep 2016
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 13 Jun 201616 Jun 2016

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2016-September
ISSN (Print)0743-1562

Conference

Conference36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/TerritoryUnited States
CityHonolulu
Period13/06/1616/06/16

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