A new memory-reduced architecture design for log-MAP algorithm in turbo decoding

Tsung Han Tsai; Cheng Hung Lin

A new memory-reduced architecture design for log-MAP algorithm in turbo decoding

Tsung Han Tsai, Cheng Hung Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This paper presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.

Original language	English
Title of host publication	Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies
Subtitle of host publication	Frontiers of Mobile and Wireless Communication
Pages	607-610
Number of pages	4
State	Published - 2004
Event	Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication - Shanghai, China Duration: 31 May 2004 → 2 Jun 2004

Publication series

Name	Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
Volume	2

Conference

Conference	Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication
Country/Territory	China
City	Shanghai
Period	31/05/04 → 2/06/04

Cite this

Tsai, T. H., & Lin, C. H. (2004). A new memory-reduced architecture design for log-MAP algorithm in turbo decoding. In Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication (pp. 607-610). (Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication; Vol. 2).

Tsai, Tsung Han ; Lin, Cheng Hung. / A new memory-reduced architecture design for log-MAP algorithm in turbo decoding. Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication. 2004. pp. 607-610 (Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication).

@inproceedings{534b3f9a0d3f4b18acbee9622384ad40,

title = "A new memory-reduced architecture design for log-MAP algorithm in turbo decoding",

abstract = "In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This paper presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.",

author = "Tsai, {Tsung Han} and Lin, {Cheng Hung}",

year = "2004",

language = "???core.languages.en_GB???",

isbn = "0780379381",

series = "Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication",

pages = "607--610",

booktitle = "Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies",

note = "null ; Conference date: 31-05-2004 Through 02-06-2004",

}

Tsai, TH & Lin, CH 2004, A new memory-reduced architecture design for log-MAP algorithm in turbo decoding. in Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication. Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication, vol. 2, pp. 607-610, Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication, Shanghai, China, 31/05/04.

A new memory-reduced architecture design for log-MAP algorithm in turbo decoding. / Tsai, Tsung Han; Lin, Cheng Hung.

Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication. 2004. p. 607-610 (Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A new memory-reduced architecture design for log-MAP algorithm in turbo decoding

AU - Tsai, Tsung Han

AU - Lin, Cheng Hung

PY - 2004

Y1 - 2004

N2 - In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This paper presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.

AB - In coding theory, turbo codes have been the breakthrough in recent years. Among these, the MAP (maximum a posteriori) algorithm is a powerful SISO (soft-input soft-output) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This paper presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without extra address generators.

UR - http://www.scopus.com/inward/record.url?scp=20344399414&partnerID=8YFLogxK

M3 - 會議論文篇章

AN - SCOPUS:20344399414

SN - 0780379381

T3 - Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication

SP - 607

EP - 610

BT - Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies

Y2 - 31 May 2004 through 2 June 2004

ER -

Tsai TH, Lin CH. A new memory-reduced architecture design for log-MAP algorithm in turbo decoding. In Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication. 2004. p. 607-610. (Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication).

A new memory-reduced architecture design for log-MAP algorithm in turbo decoding

Abstract

Publication series

Conference

Fingerprint

Cite this