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A new logic synthesis and optimization procedure
K. H. Cheng
, V. C. Hsieh
Department of Electrical Engineering
Research output
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peer-review
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Keyphrases
Area-efficient
50%
Circuit Optimization
50%
Design Procedure
50%
Family-centered
50%
High Performance
50%
Logic Circuit
50%
Logic Family
50%
Logic Functions
50%
Logic Optimization
100%
Logic Synthesis
100%
Low Power
50%
Low Power Consumption
50%
Low Voltage
50%
Optimization Procedure
100%
Power Delay Product
50%
Proposed Design
50%
Synthesis Methods
100%
Computer Science
Design Procedure
100%
Logic Family
100%
Logic Synthesis
100%
Low Power Consumption
100%
Supply Voltage
100%
Engineering
Design Procedure
50%
Logic Circuit
100%
Logic Function
50%
Logic Synthesis
100%
Low Power Consumption
50%
Optimisation Procedure
100%
Supply Voltage
50%
Mathematics
Logic Function
50%
Low Power
100%